Memristor AI chips: how in-memory and neuromorphic computing work

What a memristor is

In September 1971, Leon Chua proposed a fourth basic circuit element in IEEE Transactions on Circuit Theory, to sit beside the resistor, the capacitor and the inductor. He called it the memristor, short for memory resistor, and defined it by a relationship between electric charge and flux linkage, the running total of voltage over time. In practical terms, a memristor is a resistor whose resistance depends on how much charge has already flowed through it, and in which direction. Chua built working laboratory models out of active circuits, but no physical device of this kind was known.

That changed in May 2008, when four HP Labs researchers published "The missing memristor found" in Nature. They showed that memristance arises naturally in nanoscale devices where electronic current and the movement of charged atoms are coupled under an applied voltage, and pointed to titanium dioxide cross-point switches as an example. Drive current one way and the atoms shift so the device conducts better; drive it the other way and it conducts worse. Where those atoms sit is the memory.

Many memristors used in AI research are thin oxide films between two electrodes: titanium dioxide at HP, tungsten oxide in a 2017 University of Michigan experiment, and an oxide of five metals in the 2024 study below. Resistive RAM (RRAM) works on the same principle: its conductance depends on a filament formed by the movement of just a few atoms, as IBM researchers explain in IEEE Spectrum. IBM's own analog AI chips use a close relative, phase-change memory (PCM), whose conductance depends on how much of a tiny region is crystalline rather than amorphous.

Two properties make these devices interesting for AI hardware:

• Many levels, kept without power. A device can be set to a range of conductances rather than only 0 or 1, and non-volatile types keep that value when the power is off. One device can therefore hold one neural-network weight.
• A memory that fades. Some memristors are deliberately volatile: a pulse lowers their resistance, which then rises again over time. That fading trace lets them respond to timing, the property behind the 2024 headline.

The first property leads to in-memory computing. The second leads to memristors that keep time.

Why AI chips want to compute in memory

Running a neural network is mostly one operation repeated billions of times: multiply an input by a weight and add the product to a running total, a multiply-accumulate (MAC). The arithmetic is cheap. Fetching the numbers is not. In their tutorial and survey of deep neural network hardware (Proceedings of the IEEE, December 2017), Vivienne Sze and colleagues at MIT note that each MAC needs three memory reads and one write, and that a DRAM access can cost orders of magnitude more energy than the computation. In their figures for an accelerator's memory hierarchy, feeding a MAC from off-chip DRAM costs about 200 times the energy of the MAC itself, against 6 times from an on-chip buffer, 2 times from a neighbouring processing element (PE) and about the same as the MAC from a small register file beside the arithmetic unit.

IBM Research notes that nearly all modern processors follow the von Neumann architecture, with memory physically separate from processing. The time and energy spent shuttling data between the two is the von Neumann bottleneck. It shows up in the AI people use every day: NVIDIA's guide to LLM inference optimization explains that when a large language model generates text one token at a time, the speed at which weights and cached keys and values move from memory to the GPU sets the latency, not the arithmetic. The step is memory-bound.

Hardware designers have two ways out. The first keeps standard transistor circuits, made in ordinary chip processes, but puts memory right beside every compute unit: IBM's NorthPole and Intel's Loihi chips work this way. The second goes further and makes the memory do the arithmetic in analog form, which is where memristors come in.

How analog in-memory computing works

The building block is a crossbar: a grid of rows and columns with a memristor at every crossing. Each device's conductance holds one weight of a network layer. To compute that layer, the chip turns the inputs into voltages, or pulses of a set length, on the rows. By Ohm's law, the current through each device is the voltage times its conductance: one multiplication. By Kirchhoff's current law, the currents flowing into each column add up: the accumulation. One read of the array performs a whole matrix-vector multiplication in place, and converters at the end of each column turn the summed currents back into digital numbers, as the IBM team describes in IEEE Spectrum.

Weights can be negative and conductances cannot, so a weight is usually stored as the difference between two devices, one adding current and one subtracting it. The weights never leave the array; only the inputs and results travel.

Research teams have built working chips on this principle:

Each paper reports an efficiency gain on the workloads it tested: the Tsinghua team reported more than two orders of magnitude better energy efficiency than state-of-the-art GPUs on its network, and NeuRRAM twice the efficiency of earlier RRAM compute-in-memory chips. All three are research chips.

Where analog accuracy breaks down

Analog computing is only approximately right. A 2023 IBM study in Nature Communications says so plainly: an analog array computes matrix-vector multiplications approximately, because of imperfections that are often random or nonlinear, and that can cost accuracy. The errors come from several places:

Two limits matter most in practice. First, writing a PCM or RRAM device precisely is slow, and these devices wear out after fewer write cycles than SRAM or DRAM, according to the IBM researchers. That suits inference, where weights rarely change, far better than training. Second, precision is modest: NeuRRAM matched software models quantized to 4-bit weights, not full-precision ones. Neural networks tolerate that: many already run well at 8-bit or even 4-bit precision on digital hardware.

The main remedy is hardware-aware training: train the model with the chip's imperfections simulated, so it learns weights that survive them. In the 2023 IBM study, many larger networks, including convolutional networks, recurrent networks and transformers, could be retrained to match floating-point accuracy in simulation. Five of the eleven workloads tested stayed within 1% of the floating-point result even after an hour of conductance drift; the rest missed that target, which the authors read as a need for better devices. Noise added to inputs and outputs hurt accuracy more than noise in the weights.

What the 2024 "memristors mimic neural timekeeping" study showed

The study behind the headline is "Efficient data processing using tunable entropy-stabilized oxide memristors" by Sangmin Yoo, Sieun Chae and colleagues, with Wei Lu and John Heron of the University of Michigan as corresponding authors. Nature Electronics published it on May 20, 2024, in its June issue (volume 7, pages 466 to 474). Researchers at the University of Oklahoma, Cornell University and Pennsylvania State University took part, and the National Science Foundation funded the work, according to the university's announcement.

The biology it borrows from is simple. A neuron fires only when enough input arrives within a window of time; if too much time passes, the charge it collected leaks away and the neuron relaxes. Networks of neurons that relax at different rates can make sense of sequences of events. A dynamic memristor behaves in a similar way: a pulse lowers its resistance so the next pulse passes more easily, and over time the resistance rises again. That return is its relaxation.

The problem the team tackled is control. Most memristors are made from amorphous materials, whose switching dynamics are hard to tune systematically. The team grew single-crystal films of an entropy-stabilized oxide, a mix of magnesium, cobalt, nickel, copper and zinc oxides, on an epitaxial bottom electrode of YBCO, a superconductor chosen for its crystal structure rather than its superconductivity. Changing the magnesium fraction from 0.11 to 0.27 set the devices' time constants anywhere from 159 to 278 nanoseconds.

They put the devices to work in reservoir computing. A reservoir is a fixed system with short-term memory that turns a signal arriving over time into a richer set of states; only a simple readout layer on top is trained, which keeps training cheap. Lu's group had shown the idea in hardware in 2017 with a reservoir of just 88 tungsten-oxide memristors. With reservoirs whose timing could now be tuned, the 2024 system classified time-series data with better accuracy and energy efficiency than earlier reservoir implementations. The university describes a small network that learned to recognize spoken digits from zero to nine and could name each one before the audio had finished.

What the study does not show matters as much:

• It is a device result, not a chip. The network was small, and the crystals were grown with an energy-intensive process chosen for precise measurement. The team expects a simpler process could work for mass manufacturing, and Heron described scalable production as a vision so far.
• The large energy figures are projections. The announcement says memristors could cut AI's energy needs by about a factor of 90 compared with today's GPUs, and a co-author anticipated a sixfold efficiency gain over the best material without tunable time constants. Neither figure was measured on an AI chip in this study.
• Mind the units. The time constants are nanoseconds, billionths of a second. The university's release calls them trillionths, which is a slip; the paper gives nanoseconds.

Spiking and neuromorphic chips

Neuromorphic computing designs chips after the brain rather than after the CPU. Chips such as Intel's Loihi run spiking neural networks (SNNs): neurons send brief events, spikes, only when they have something to signal, operate asynchronously, keep their memory beside the computation and talk to each other directly rather than through a shared memory. Because work happens only when spikes arrive, sparse activity costs little energy. Loihi 2 and IBM's brain-inspired NorthPole are both built in standard chip processes, not from memristors. For software that imitates how people decide, see human-like AI and confidence.

Intel Loihi 2 and Hala Point

Intel introduced Loihi 2, its second-generation neuromorphic research chip, on September 30, 2021. It supports up to 1 million neurons per chip, was made on a pre-production version of the Intel 4 process, and came with Lava, an open-source software framework for neuromorphic applications. At launch, Intel offered Loihi 2 systems to members of its Intel Neuromorphic Research Community through a research cloud.

On April 17, 2024, Intel announced Hala Point, which packs 1,152 Loihi 2 processors into a six-rack-unit data center chassis. It supports up to 1.15 billion neurons and 128 billion synapses across 140,544 neuromorphic cores and draws at most 2,600 watts. Intel reports up to 20 quadrillion operations per second and more than 15 trillion 8-bit operations per second per watt on conventional deep neural networks, without collecting inputs into batches the way GPUs usually do. It was first deployed at Sandia National Laboratories, and Intel called it a research prototype.

IBM NorthPole

NorthPole, which IBM Research unveiled with a paper in Science in October 2023, takes the near-memory route in digital logic. It is made in a 12 nm process with 22 billion transistors and 256 cores, and all of its memory is on the chip, interleaved with the compute. On the ResNet-50 image model, IBM measured 25 times more frames per joule than common 12 nm GPUs and 14 nm CPUs. The same design is also its constraint: NorthPole is only for inference, and it is fast only while a model fits in its on-chip memory, so larger networks are split across several chips.

In September 2024, IBM reported running a 3-billion-parameter language model derived from its Granite code model on 16 NorthPole cards in a standard 2U server, with latency below 1 millisecond per token. In a November 2024 overview of its AI chips, IBM still described NorthPole as a research prototype that clients can evaluate, called its analog chips the most experimental of the family, and named Spyre, a 32-core accelerator card for IBM Z systems, as the commercial product.

Neuromorphic chips you can buy

Small neuromorphic chips do ship. BrainChip, for example, sells the AKD1500, a neuromorphic co-processor that pairs with a host CPU or microcontroller over PCIe or SPI, for low-power inference in IoT, industrial, automotive and medical devices (as of September 2026). These are edge parts for sensing tasks, not replacements for a data center GPU.

Treat efficiency figures across these chips with care. A chip-sustained figure for IBM's analog chip, a system figure for Hala Point and a frames-per-joule result for NorthPole come from different models, precisions and measurement boundaries. They show direction, not a ranking.

How far these chips are from the GPUs and NPUs that run AI today

Four gaps separate the research rows from the shipping ones:

• Scale. IBM's analog demonstration spread a speech model of more than 45 million weights over five chips, while its own paper notes that current AI models have billions of parameters. NorthPole's language-model demonstration used 16 cards for 3 billion parameters, one transformer layer per card.
• Inference only. NorthPole is built for inference, and analog devices are slow to write and wear out, which makes the constant weight updates of training much harder.
• Software and models. Analog chips need models retrained for their noise, and Loihi runs its own framework, Lava. GPUs and NPUs run standard models through the frameworks developers already use.
• Manufacturing. Michigan's crystals were grown for measurement, not production. TSMC does produce embedded RRAM in high volume at 40, 28, 22 and 12 nm, as an alternative to embedded flash, which shows the material family can be made at scale. Storing digital bits reliably is a simpler job than holding precise analog weights that must not drift, though.

What this means if you run AI today

For anyone deploying AI in 2026, the practical choices are digital: GPUs in a data center or cloud account, and NPUs in recent laptops and other devices. Microsoft, for example, requires an NPU that performs more than 40 trillion operations per second for many Windows AI features on Copilot+ PCs. Nothing in this research changes that choice this year.

The research still explains what to watch in the hardware you can use:

1. Memory is usually the limit, not arithmetic. Text generation in a language model is memory-bound, so model size and memory bandwidth set the speed. Smaller and quantized models help because they move fewer bytes; our AI frameworks comparison covers quantization and the runtimes that support it.
2. Put inference where latency and privacy need it. A small model on a device's NPU avoids a network round trip and keeps data on the device, at the cost of model size. Our guide to intelligent apps weighs on-device against cloud inference.
3. Read efficiency claims by their boundaries. Ask whether a figure covers one tile, one chip or a whole system, on which model and at what precision.
4. Look for results on full systems and current models. NorthPole's move from an image model in 2023 to a 3-billion-parameter language model in 2024 is the kind of step that matters; a single device with a better time constant is not yet a product.

If you are deciding where AI belongs in your own work, the chip underneath matters less than whether the answers are right and what each run costs. Our AI automation service starts with a working prototype on your real cases, scored against a success test and costed per case, and builds for production only when the prototype meets the agreed scores.